By Bramhananda Marathe,Sandhya Nerale
The goal of this ebook is to supply perception and instinct into the analog and analog-mixed sign procedure verification. it's also a trip the writer of this booklet has been via with the intention to take on sensible layout and verification demanding situations with kingdom of artwork analog and combined sign designs.
Motivation for authoring this book
The electronic layout verification ability set is especially assorted than analog layout and verification. normally, the analog block point verification is played via the analog designers, and electronic layout verification is played via electronic layout verification engineer. loss of move area ability set makes it hard to accomplish verification at mixed-signal point. therefore, both analog dressmaker engineer should still research complicated electronic verification recommendations or electronic layout verification engineer include analog verification to turn into analog-mixed sign verification engineer. This ebook is written preserving this new pattern in brain, therefore it covers electronic layout basics, electronic layout verification in addition to analog layout basics, and analog functionality verification.
Organization of this book
Keeping the readers of analog verification or electronic layout verification heritage in brain, the publication has first five chapters all for the basics of the analog layout, electronic layout, and its verification. bankruptcy 6 and bankruptcy 7 makes a speciality of the analog-mixed sign layout verification and behavioral modeling respectively. bankruptcy eight is devoted to the low strength verification recommendations.
Chapter 1: creation to Analog combined sign Verification
This bankruptcy discusses in regards to the evolution of the verification methodologies, background of analog-mixed sign designs, functions, and destiny developments.
Chapter 2: Analog layout basics
The goal of this bankruptcy is to provide an outline of the analog layout basics for electronic layout heritage engineers. significant concentration is given on analog habit, layout standards and their idea instead of layout themselves, resembling voltage/current reference, many of the easy key analog layout homes equivalent to achieve, band width, fundamentals of jitter, eye diagram, and so forth.
Chapter three: electronic layout basics
In this bankruptcy, we clarify electronic layout move, combinational and sequential good judgment layout basics, layout for testability, suggestions of timing, and timing verification.
Chapter four: Analog Verification
This bankruptcy specializes in analog functionality verification and sensible verification below the context of combined sign layout hierarchical verification instead of the aspect functionality research of the designs themselves.
Chapter five: electronic layout Verification
This bankruptcy explains the instruments and methodologies which are developed over the interval which are predicated on predictable caliber and verification potency. The bankruptcy includes the sections at the insurance pushed verification (CDV) method, statement established verification (ABV) method, and evaluation of the CDV utilizing Open Verification method (OVM).
Chapter 6: Analog-Mixed sign Verification
This bankruptcy discusses in regards to the AMS verification stages, selecting the right abstraction of DUT for a given verification problem, AMS verification making plans, testplanning for AMS layout verification, and testbench improvement with re-use in brain.
Chapter 7: Analog Behavioral Modeling
This bankruptcy explains in regards to the functions of analog behavioral versions, modeling technique, basic examples of assorted analog behavioral modeling types, choice of accuracy point of the versions in accordance with the verification plan, version verification, and signoff.
Chapter eight: Low strength Verification
The function of this bankruptcy is to give an explanation for the low energy layout verification demanding situations, key low strength layout parts, low strength layout ideas, low energy layout and verification cycle, testplanning for low strength layout verification, energy conscious electronic, and AMS simulations
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Additional resources for Analog-Mixed Signal Verification
Analog-Mixed Signal Verification by Bramhananda Marathe,Sandhya Nerale